The present invention relates to an overflow detector for algebraic adders.
When calculating with algebraic, i.e., positive and negative, binary numbers, these numbers are usually provided with a sign digit which characterizes them as positive or negative. Positive binary numbers are commonly designated by the sign digit 0, and negative ones are designated by the sign digit 1. Since, in algebra, no distinction is made between the rules of addition and those for subtraction, but only the rule of addition is applied to positive and negative numbers, negative binary numbers are represented and added in two's complement, for example; this eliminates the need to switch the adder to subtraction and reduces the complexity of the circuit. Subtraction is thus performed by adding the two's complement of the subtrahend by means of the same full adder as that used for addition.
If two numbers with like signs are added, the capacity of the number representation may be exceeded, so that the result becomes invalid. If the numbers to be added are positive, the sum will also be positive, but if the sign digit is a 1 instead of a 0 and, thus, falsely makes the result appear as a negative number, a positive "overflow" has arisen.
If both the augend and the addend are negative, the result is also negative; the occurrence of a 0 instead of a 1 in the sign position characterizes a "negative" overflow.
The respective false digit is caused by the carry signal c coming from the most significant full adder. In both cases of overflow, the (false) change of state in the sign position not only results in a false sign but falsifies the whole result, because a positive number with a "false" negative sign also has a false numerical value.
According to a book by U. Tietze, Ch. Schenk, "Halbleiterschaltungstechnik", 5th Edition, Springer-Verlag Berlin, Heidelberg, New York, 1980, page 482, the following equation holds for the overflow signal fl: EQU fl=va.multidot.vb.multidot.vs+va.multidot.vb.multidot.vs
An overflow detector implemented in accordance with this equation using MOS technology consists of a complex gate made up of two NORed three-input AND elements and followed by an inverter. Such a circuit is slow because the delay is determined by two gates connected in series with respect to the signal flow.